1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
In recent years, as the result of a reduction in power consumption of the mobile equipment, and the like, a demand for lower power consumption in semiconductor devices such as LSIs, and so on, which are incorporated into the equipment, is increasing. As the semiconductor device capable of meeting such demand, there is the MOS transistor having the dual gate structure. The dual gate structure is a MOS transistor having such a structure that an n-type impurity is introduced into a gate electrode of an n-type MOS transistor and a p-type impurity is introduced into a gate electrode of a p-type MOS transistor. A threshold voltage of the transistor can be lowered if the same impurity as the conductivity type of the channel is introduced into the gate electrode in this manner, and thus the power consumption of the transistor can be suppressed.
However, only a single kind of dual gate transistor of the identical driving voltage is rarely integrated in an actual semiconductor device. Commonly, the transistor having the dual gate structure is employed as the normal transistor for the logic circuit whose driving voltage is low, and this normal transistor is embedded with a high-voltage transistor. For instance, in the driver IC in the liquid crystal panel, the high-voltage driving transistor used to apply a voltage to alignment electrodes of the liquid crystal panel is formed together with the normal transistor for the logic circuit.
The semiconductor device in which the normal transistor having such dual gate structure and the high-voltage transistor are integrated together is disclosed in FIG. 32 in Patent Literature 1.
FIG. 1 to FIG. 4 are sectional views showing the essential part of processes in a method of manufacturing a semiconductor device disclosed in Patent Literature 1.
First, as shown in FIG. 1A, element isolation insulating films 2 are buried in element isolation trenches 1a of a silicon substrate 1, and then a thermal oxide film 3 and an undoped polysilicon film 4 are formed sequentially on the silicon substrate 1.
A normal transistor forming region I and a high-voltage transistor forming region II are defined on the silicon substrate 1. The thermal oxide film 3 in the high-voltage transistor forming region II is formed thicker than that in the normal transistor forming region I.
Then, as shown in FIG. 1B, first to fourth gate electrodes 4a to 4d are formed by patterning the polysilicon film 4.
Then, as shown in FIG. 1C, first to fourth n-type source/drain extensions 5a to 5d and first to fourth p-type source/drain extensions 5e to 5h are formed by the ion implantation using the first to fourth gate electrodes 4a to 4d as a mask. In this case, individual implantations of the p-type impurity and the n-type impurity in this ion implantation are executed by using resist patterns (not shown), and then the resist patterns are removed after the ion implantation is ended.
Then, as shown in FIG. 1D, an insulating film 6 is formed on the overall surface, and then a resist pattern 7 is formed on the insulating film 6 in the high-voltage transistor forming region II. The resist pattern 7 has first and second windows 7c, 7d on the gate electrodes 4c, 4d respectively. In contrast, the normal transistor forming region I is not covered with the resist pattern 7 and is exposed.
Then, as shown in FIG. 1E, the insulating film 6 is etched back while using the resist pattern 7 as a mask. Thus, the insulating film 6 is shaped into an insulating sidewall 6a positioned besides the first to fourth gate electrodes 4a to 4d respectively, and also the thermal oxide film 3 located under the gate electrodes 4a to 4d is shaped into first to fourth gate insulating films 3a to 3d respectively. Also, the insulating film 6 under the first and second windows 7c, 7d is etched by the etching-back. Thus, first and second openings 6c, 6d are formed in the insulating sidewall 6a and thus upper surfaces of the third and fourth gate electrodes 4c, 4d are exposed from these openings 6c, 6d. 
Also, out of the gate electrodes 4a to 4d, an extended portion 6b that corresponds to the resist pattern 7 is formed to extend from the insulating sidewall 6a positioned besides the third and fourth gate electrodes 4c, 4d in the high-voltage transistor forming region II respectively.
Meanwhile, prior to this step, the thermal oxide film 3 is formed in the high-voltage transistor forming region II to have a thickness that is thicker than that in the normal transistor forming region I. For this reason, in the etching-back step, even if an etching time is set to remove completely the thermal oxide film 3 and the insulating film 6 from the normal transistor forming region I, it is possible that the etching is not completed owing to the etching residue of the thick thermal oxide film 3 in the high-voltage transistor forming region II and the thermal oxide film 3 still remains on the silicon substrate 1.
Therefore, in order not to leave the thermal oxide film 3 in the high-voltage transistor forming region II, an etching time is set in the etching-back step such that the thermal oxide film 3 and the insulating film 6 can be removed completely from the high-voltage transistor forming region II.
However, the over-etching is caused by such etching time in the normal transistor forming region I in which the thermal oxide film 3 is formed thin. Thus, as shown in FIG. 1E, upper surfaces of the element isolation insulating films 2 are etched and their height is lowered than that of the silicon substrate 1.
Then, as shown in FIG. 1F, a resist pattern (not shown) having windows from which n-type MOS transistor forming regions are exposed is formed. Then, the n-type impurity is ion-implanted simultaneously into the silicon substrate 1 and the first and third gate electrodes 4a, 4c through the windows. As a result, first to fourth n-type source/drain region 8a to 8d are formed in the silicon substrate 1 on the side of the gate electrodes 4a, 4c, and also the conductivity type of the gate electrodes 4a, 4c is set to the n type. Also, according to the same processes as above, first to fourth p-type source/drain regions 8e to 8h are formed and at the same time the conductivity type of the gate electrodes 4b, 4d is set to the p type.
In this ion implantation, since the impurity is blocked by the insulating sidewalls 6a, the source/drain regions 8a to 8h are not formed in the silicon substrate 1 under the insulating sidewalls 6a, and thus the source/drain extensions 5a to 5h are still extended thereunder. The source/drain extensions 5a to 5h in the area in which the source/drain regions 8a to 8h are not formed are called the offset.
Then, as described above, since the extended portion 6b is provided to the insulating sidewall 6a in the high-voltage transistor forming region II, an offset W2 in the high-voltage transistor forming region II becomes longer than an offset W1 in the normal transistor forming region I.
According to the steps applied up to now, basic structures of an n-type MOS transistor TRn and a p-type MOS transistor TRp having the dual gate structure are completed in the normal transistor forming region I respectively. In contrast, basic structures of an n-type high-voltage MOS transistor TR(high)n and a p-type high-voltage MOS transistor TR(high)p are completed in the high-voltage transistor forming region II. In the high-voltage MOS transistors TR(high)n and TR(high)p, since a source-drain interval is prolonged by the offset W2 that is longer than the offset W1 of the normal transistor, a source-drain withstand voltage can be enhanced. Also, since the gate insulating films 3c, 3d are formed thicker than the gate insulating films 3a, 3b of the normal transistor, a gate-source withstand voltage can be enhanced.
Then, as shown in FIG. 1G, a refractory metal layer is formed on the overall surface and then the refractory metal layer is caused to react with the silicon by the annealing. Thus, a silicide layer 9 is formed on the source/drain regions 8a to 8h and the gate electrodes 4a to 4d. Then, the unreacted refractory metal layer is removed by the etching.
Then, as shown in FIG. 1H, an interlayer insulating film 10 is formed on the overall surface and is patterned. Thus, first to eighth holes 10a to 10h are formed on the source/drain region 8a to 8h, and also first to eighth conductive plugs 11a to 11h are buried in the holes 10a to 10h. 
With the above, a basic structure of the semiconductor device in the prior art is completed.
According to the above prior art, as explained with reference to FIG. LE, due to a difference in the thermal oxide films 3 in respective regions I and II, the element isolation insulating films 2 in the normal transistor forming region I are etched at the time of forming the sidewall insulating films 6a, and thus their height is lowered than the upper surface of the silicon substrate 1.
However, when the element isolation insulating films 2 are etched in this manner, the silicide layer 9 is also formed on the silicon substrate 1 exposed on the side surface of the element isolation trench 1a, as shown in FIG. 2. Thus, the first n-type source/drain region 8a and the silicon substrate 1 are short-circuited by the silicide layer 9. As a result, it is impossible to control an electric potential of the first n-type source/drain region 8a via the first conductive plug 11a. 
Also, in the ion-implantation step shown in FIG. 1F, as shown in an enlarged sectional view of FIG. 3, the n-type impurity is injected into the third gate electrode 4c through the first opening 6c in the insulating sidewall 6a, and thus a resistance of the third gate electrode 4c is lowered.
In this case, it is only a doped portion 4e of the third gate electrode 4c in the first opening 7c indicated by the hatching that the n-type impurity is injected into. Thus, the n-type impurity is not injected into the portions covered with the insulating sidewalls 6a, and these portions are left as undoped portions 4f. 
However, when viewed from the carriers flowing through a channel 13, the carriers are influenced by the voltage of the third gate electrode 4c under the doped portion 4e whereas the influence of the gate electrode is reduced under the undoped portion 4f. Thus, the same effect as the case where the gate insulating film 3c only under the undoped portion 4f is made locally thick appears. According to this, a threshold voltage under the undoped portion 4f is increased higher than that under the doped portion 4e and therefore a channel resistance is increased and also a driving ability of the transistor TR(high)n is lowered.
In addition, the channel resistance depends on a shape and a size of the undoped portion 4f. Therefore, the channel resistance is changed depending upon a positional displacement between the first opening 7c and the third gate electrode 4c and thus there is a possibility that the driving ability is varied among a plurality of transistors.
Further, in the silicide step shown in FIG. 1G, as shown in an enlarged sectional view of FIG. 4, it is only in the portion under the first opening 7c of the insulating sidewall 6a that the silicide layer 9 is formed on the upper surface of the third gate electrode 4c. Thus, the silicide layer 9 is not formed in the portion covered with the insulating sidewall 6a, and the resistance of the third gate electrode 4c cannot be sufficiently lowered.
The high-voltage transistors are also disclosed in Patent Literatures 2, 3.
In Patent Literature 2, the structure capable of extending the offset of the source/drain extension by employing the dual sidewall in which two sidewalls are stacked is proposed. However, a width of the inner sidewall constituting the dual sidewall is almost 100 nm roughly, and only a width of 0.2 μm is given at most by the dual sidewall. For this reason, the width of the source/drain extension cannot be sufficiently expanded by the structure in Patent Literature 2 and thus it becomes difficult to increase sufficiently the source-drain withstand voltage of the high-voltage transistor.
Also, in Patent Literature 3, the process of forming the thermal oxide film on side walls and the upper surface of the gate electrode and then removing the thermal oxide film only from the upper surface to form the silicide layer therein is proposed. However, the thick thermal oxide film cannot be formed on the side surfaces of the gate electrode. Therefore, like Patent Literature 2, the width of the source/drain extension cannot be sufficiently expanded and thus the source-drain withstand voltage cannot be enhanced.
In addition to the above, the technology to integrate together the normal transistor and the high-voltage transistor is also disclosed in Patent Literatures 4 to 10.
[Patent Literature 1] Patent Application Publication (KOKAI) 2000-196037
[Patent Literature 2] Patent Application Publication (KOKAI) 2001-93984
[Patent Literature 3] Patent Application Publication (KOKAI) 2002-26139
[Patent Literature 4] Patent Application Publication (KOKAI) Hei 10-242414
[Patent Literature 5] Patent Application Publication (KOKAI) 2000-299390
[Patent Literature 6] Patent Application Publication (KOKAI) Sho 55-63873
[Patent Literature 7] Patent Application Publication (KOKAI) Hei 3-242977
[Patent Literature 8] Patent Application Publication (KOKAI) Hei 7-263705
[Patent Literature 9] Patent Application Publication (KOKAI) Hei 5-175228
[Patent Literature 10] Patent Application Publication (KOKAI) Hei 4-279033